Login / Signup
A method for debugging of pipelined processors in formal verification by correspondence checking.
Miroslav N. Velev
Ping Gao
Published in:
ASP-DAC (2010)
Keyphrases
</>
detection method
formal verification
computational complexity
computational cost
pairwise
significant improvement
dynamic programming
probabilistic model
model checking
image matching
feature matching
image sequences
support vector machine
edge detection