A scalable LDPC decoder ASIC architecture with bit-serial message exchange.
Tyler L. BrandonRobert HangGary BlockVincent C. GaudetBruce F. CockburnSheryl L. HowardChristian GiassonKeith BoylePaul GoudSiavash Sheikh ZeinoddinAnthony RapleyStephen BatesDuncan G. ElliottChristian SchlegelPublished in: Integr. (2008)
Keyphrases
- hardware architecture
- hardware implementation
- design methodology
- message exchange
- ldpc codes
- low density parity check
- fpga implementation
- xilinx virtex
- distributed video coding
- distributed source coding
- low complexity
- turbo codes
- decoding algorithm
- computational complexity
- successive approximation
- web services
- analog to digital converter
- rate allocation
- design considerations
- compressive sensing
- integrated circuit
- application specific
- signal processing
- motion estimation