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A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes.
Euncheol Kim
Nikhil Jayakumar
Pankaj Bhagawat
Anand Selvarathinam
Gwan Choi
Sunil P. Khatri
Published in:
ICASSP (3) (2006)
Keyphrases
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ldpc codes
high speed
decoding algorithm
error correction
low density parity check
message passing
rate allocation
low power
image transmission
low cost
channel coding
frame rate
real time
turbo codes
source coding
end to end
non binary
error detection
error resilient
coding scheme
distributed systems