Scalable Full Hardware Logic Architecture for Gradient Boosted Tree Training.
Tamon SadasueTsuyoshi IsshikiPublished in: FCCM (2020)
Keyphrases
- hardware architecture
- real time
- digital circuits
- software implementation
- vlsi architecture
- vlsi implementation
- low cost
- hardware implementation
- tree structure
- feedforward artificial neural networks
- pipeline architecture
- parallel architecture
- hardware design
- training process
- computer systems
- hardware and software
- training algorithm
- software architecture
- commodity hardware
- management system
- scalable distributed
- training set
- content addressable
- host computer
- hardware architectures
- hardware software
- random forests
- fpga technology
- discriminatively trained
- dedicated hardware
- reasoning engine
- supervised learning
- data flow
- commercial off the shelf
- multithreading
- logic programming
- processing elements
- boosted classifiers
- index structure
- b tree
- neural network