A self-reconfiguration scheme for fault-tolerant VLSI processor arrays.

Stephen Pateras Janusz Rajski

Published in: ICCD (1988)

Keyphrases

fault tolerant
fault tolerance
key distribution
high speed
distributed systems
single chip
load balancing
state machine
vlsi implementation
parallel processing
high availability
signal processing
fault isolation
modular robots
chip design
error detection
focal plane
safety critical
mobile agent system
gate array