A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface.
Changhyun KimKye-Hyun KyungW.-P. JeongJ.-S. KimByung-Sik MoonJoon-Wan ChaiS.-M. YimJung-Hwan ChoiK.-H. HanC.-J. ParkHong-Sun HwangH. ChoiSung-Burn ChoClemenz L. PortmannSoo-In ChoPublished in: IEEE J. Solid State Circuits (1999)