An LSI implementation of the simple serial synchronized multistage interconnection network.

Takayuki Kamei Masashi Sasahara Hideharu Amano

Published in: ASP-DAC (1997)

Keyphrases

multistage
interconnection networks
single stage
dynamic programming
stochastic programming
production system
fault tolerant
parallel algorithm
lot sizing
latent semantic indexing
parallel computers
machine learning
message passing
routing algorithm
parallel implementation