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Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.

Kaisheng MaHuichu LiuYang XiaoYang ZhengXueqing LiSumeet Kumar GuptaYuan XieVijaykrishnan Narayanan
Published in: ISVLSI (2014)
Keyphrases
  • leakage current
  • design process
  • real time
  • digital images
  • high speed
  • silicon dioxide