Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.
Vijay K. JainGlenn H. ChapmanPublished in: DFT (2006)
Keyphrases
- signal processing
- energy consumption
- digital signal processing
- digital signal processor
- energy minimization
- low power
- energy efficiency
- low energy
- three dimensional
- hardware and software
- systolic array
- neural network
- digital plane
- high energy
- real time image processing
- failure modes
- heterogeneous networks
- heterogeneous data
- wireless sensor networks
- moving objects
- image processing