A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
Wei-Hsing HuangTai-Hao WenJe-Min HungWin-San KhwaYun-Chen LoChuan-Jia JhangHuna-Hsi HsuYu-Hsiana ChinYu-Chiao ChenChuna-Chuan LoRen-Shuo LiuKea-Tiong TangChih-Cheng HsiehYu-Der ChihTsung-Yung Jonathan ChangMeng-Fan ChangPublished in: ISSCC (2023)
Keyphrases
- memory management
- intel xeon
- memory hierarchy
- processor core
- edge information
- times faster
- edge detection
- memory subsystem
- chip design
- memory access
- processing elements
- weighted graph
- high speed
- database workloads
- multi label
- random access memory
- main memory
- memory requirements
- single chip
- computing power
- computational power
- external memory
- flash memory
- parallel processing
- edge detector
- memory usage
- cache misses
- memory bandwidth
- shared memory
- database management systems
- embedded systems
- low power
- shared memory multiprocessors
- multiscale