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Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.

Lixiang LiYuanqing LiHaibin WangRui LiuQiong WuMichael NewtonYuan MaLi Chen
Published in: J. Electron. Test. (2015)
Keyphrases
  • error tolerant
  • experimental evaluation
  • power consumption
  • nm technology
  • graph matching
  • low power
  • neural network
  • machine learning
  • pattern recognition
  • pairwise
  • low cost
  • subgraph isomorphism