Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor.
Hisashige AndoRyuji KanYoshiharu TosakaKeiji TakahisaKichiji HatanakaPublished in: DSN (2008)
Keyphrases
- circuit design
- ibm zenterprise
- error detection
- error rate
- low cost
- high speed
- hardware and software
- real time
- embedded systems
- computing power
- error correction
- instruction set
- computer systems
- computing systems
- hardware design
- memory subsystem
- special purpose hardware
- floating point arithmetic
- error analysis
- image processing
- massively parallel
- floating point
- personal computer
- error bounds
- functional verification
- learning algorithm
- neural network