Optimized Hardware Architecture of Tile to Raster Scan Buffer for Video Decoder and Display Processor.
Han-Soo SeongChoonsik JungPublished in: ICCE (2023)
Keyphrases
- hardware architecture
- raster scan
- video decoder
- xilinx virtex
- hardware implementation
- video codec
- bitstream
- connected components
- high speed
- hilbert curve
- field programmable gate array
- memory access
- video coding
- real time
- connected component labeling
- signal processing
- inter frame
- multiresolution
- high quality
- computer vision