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Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization.

Yao LuJide ZhangSu ZhengZhen LiLingli Wang
Published in: ISCAS (2022)
Keyphrases
  • low error
  • embedded systems
  • hardware implementation
  • data sets
  • training set
  • learning experience
  • hardware architecture