A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture.
Sang Min LeeDongwon SeoShahin Mehdizad TaleieDerui KongMichael Joseph McGowanTongyu SongGanesh R. SaripalliJenny KuoSeyfi S. BazarjaniPublished in: VLSIC (2015)
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