Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs.

Nazanin Mansouri Ranga Vemuri

Published in: Formal Methods Syst. Des. (2000)

Keyphrases

formal verification
model checking
model checker
symbolic model checking
bounded model checking
automated verification
sufficient conditions
semi automated
temporal logic
artificial intelligence
computer aided
generation process
source code
software components
fully automated
design tools