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DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture.

Cunlu LiDezun DongXiangke LiaoJohn KimChanghyun Kim
Published in: ICS (2019)
Keyphrases
  • buffer size
  • wide range
  • memory bandwidth
  • floating point
  • buffer allocation
  • virtual memory
  • early stage
  • response time
  • neural network
  • memory requirements
  • memory usage
  • negatively affect
  • main memory
  • loss probability