A floating-point systolic array processing element with serial communication and built-in self-test.
T. C. DaviesDhamin Al-KhaliliValek SzwarcPublished in: J. VLSI Signal Process. (1994)
Keyphrases
- floating point
- systolic array
- parallel architecture
- square root
- reconfigurable architecture
- fixed point
- data processing
- data flow
- instruction set
- built in self test
- sparse matrices
- parallel processing
- floating point arithmetic
- fast fourier transform
- distributed memory
- interval arithmetic
- low cost
- pairwise
- bayesian networks