A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC.
Vijay K. JainSanjukta BhanjaGlenn H. ChapmanLavanya DoddannagariPublished in: SoCC (2005)
Keyphrases
- systolic array
- reconfigurable architecture
- low cost
- digital signal processing
- digital signal
- general purpose
- low power
- programmable logic
- signal processing
- three dimensional
- high speed
- field programmable gate array
- parallel architecture
- computer vision
- focal plane
- digital signal processor
- hardware and software
- data flow
- real time
- real world
- data sets