A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design.

Hiroaki Yamaoka Makoto Ikeda Kunihiro Asada

Published in: ESSCIRC (2003)

Keyphrases

high speed
low power
cmos technology
digital circuits
logic circuits
logic synthesis
circuit design
user interface
chip design
neural network
shift register
focal plane
evolvable hardware
design tools
engineering design
special case
data sets
micron cmos