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A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.

Masafumi OnouchiKazuo OtsugaYasuto IgarashiToyohito IkeyaSadayuki MoritaKoichiro IshibashiKazumasa Yanagisawa
Published in: A-SSCC (2011)
Keyphrases
  • low voltage
  • transient response
  • cmos technology
  • leakage current
  • power line
  • design considerations
  • low power
  • control system
  • power consumption
  • power management