A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology.
Jian-Hao LuKe-Hou ChenShen-Iuan LiuPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2009)
Keyphrases
- analog vlsi
- high speed
- circuit design
- focal plane
- cmos image sensor
- computer simulation
- low cost
- power consumption
- low power
- mixed signal
- relevance feedback
- analog to digital converter
- successive approximation
- floating gate
- decision feedback
- analog circuits
- cmos technology
- visual feedback
- digital circuits
- topology preserving
- signal processing
- information retrieval