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A 200 MHz register-based wave-pipelined 64 M synchronous DRAM.
Ho-Jun Song
Jung-Pill Kim
Jae-Jin Lee
Jong-Hoon Oh
Seung-Han Ahn
Inseok Hwang
Published in:
IEEE J. Solid State Circuits (1997)
Keyphrases
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main memory
high speed
high density
cmos technology
low voltage
wave propagation
asynchronous communication
high frequency
data flow
databases
nearest neighbor
low power
memory subsystem
embedded dram