A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.
Ahmed M. A. AliHüseyin DincParitosh BhoraskarScott PuckettAndy MorganNing ZhuQicheng YuChristopher DillonBryce GrayJonathan LanfordMatthew McSheaUshma MehtaScott BardsleyPeter R. DerounianRyan BunchRalph MooreGerry TaylorPublished in: VLSI Circuits (2016)