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A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.
Pietro Andreani
Lars Sundström
Niklas Karlsson
M. Svensson
Published in:
ISCAS (1) (1999)
Keyphrases
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bit parallel
high speed
pattern matching
low cost
real world
chip design
circuit design
ibm power processor
complex systems
power consumption
high density
computational power
high power
power management
radio frequency
floating point
signal processing
high level