Integrating Scan Design and Soft Error Correction in Low-Power Applications.
Michael E. ImhofHans-Joachim WunderlichChristian G. ZoellinPublished in: IOLTS (2008)
Keyphrases
- low power
- error correction
- low power consumption
- high speed
- low cost
- power consumption
- single chip
- logic circuits
- vlsi architecture
- gate array
- cmos technology
- digital signal processing
- error detection
- mixed signal
- low density parity check
- error correcting
- power dissipation
- data hiding
- power reduction
- design methodology