A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications.
Robert PalmerJohn PoultonWilliam J. DallyJohn G. EylesAndrew M. FullerTrey GreerMark HorowitzMark KellamF. QuanF. ZarkeshvariPublished in: ISSCC (2007)
Keyphrases
- high speed
- cmos technology
- analog vlsi
- nm technology
- power consumption
- low cost
- low power
- ultra low power
- silicon on insulator
- circuit design
- single chip
- metal oxide semiconductor
- cmos image sensor
- chip design
- image sensor
- power supply
- power dissipation
- phase locked loop
- random access memory
- focal plane
- mixed signal
- programmable logic
- vlsi implementation
- physical design
- ibm power processor
- parallel processing
- low voltage
- evolvable hardware
- design considerations
- high density
- operating system