Login / Signup

CMOS Scaling for sub-90 nm to sub-10 nm.

Hiroshi Iwai
Published in: VLSI Design (2004)
Keyphrases
  • cmos technology
  • silicon on insulator
  • nm technology
  • metal oxide semiconductor
  • low cost
  • transmission electron microscopy
  • computer vision
  • power consumption
  • low power
  • website
  • high speed
  • parallel processing