A prototype VLSI chip architecture for JPEG image compression.
Mario KovacN. RanganathanMartin ZagarPublished in: ED&TC (1995)
Keyphrases
- vlsi implementation
- vlsi architecture
- high speed
- single chip
- vlsi design
- jpeg image compression
- processor array
- real time
- cmos image sensor
- image compression
- chip design
- host computer
- analog vlsi
- management system
- high density
- signal processing
- low cost
- modular architecture
- vlsi circuits
- level parallelism
- mixed signal
- database
- computer vision
- physical design
- design methodology
- data flow
- client server architecture
- middleware architecture
- software architecture
- design considerations
- signal processor