Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM.
Tomohiro KorikawaAkio KawabataFujun HeEiji OkiPublished in: HPSR (2019)
Keyphrases
- high density
- embedded dram
- real time
- content addressable memory
- memory subsystem
- reconfigurable hardware
- low cost
- high speed
- random access memory
- packet switching
- gigabit ethernet
- parallel architecture
- analog vlsi
- management system
- dynamic random access memory
- cmos technology
- vlsi implementation
- level parallelism
- processing units
- processing elements
- digital signal processors
- design methodology
- main memory
- low voltage
- network on chip
- multithreading
- nm technology