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Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs.
Ali Ebrahim
Khaled Benkrid
Xabier Iturbe
Chuan Hong
Published in:
AHS (2013)
Keyphrases
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field programmable gate array
hardware implementation
pattern recognition
data processing
bit rate
parallel algorithm
multiple types
xilinx virtex