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Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs.

Ali EbrahimKhaled BenkridXabier IturbeChuan Hong
Published in: AHS (2013)
Keyphrases
  • field programmable gate array
  • hardware implementation
  • pattern recognition
  • data processing
  • bit rate
  • parallel algorithm
  • multiple types
  • xilinx virtex