GaAs pseudodynamic latched logic for high performance processor cores.
José Francisco LópezKamran EshraghianRoberto SarmientoAntonio NúñezDerek AbbottPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- embedded dram
- random access memory
- multi core processors
- dynamic random access memory
- processor core
- cmos technology
- distributed memory
- parallel architectures
- memory subsystem
- highly parallel
- embedded processors
- chip design
- gallium arsenide
- multi core systems
- multicore processors
- computation intensive
- low voltage
- proof theory
- high speed
- multi core architecture
- classical logic
- operating system