A 3.3-V analog front-end chip for HomePNA applications.

Jaeyoung Shin Joongho Choi Jinup Lim Sungwon Noh Namil Baek Jong-Hyeong Lee

Published in: ISCAS (4) (2001)

Keyphrases

analog vlsi
mixed signal
circuit design
cmos image sensor
back end
low power
multi channel
high speed
focal plane
low cost
high density
single chip
parallel processing
physical design
neural network
digital circuits
databases
vlsi design
user friendly