A 12.1 TOPS/W Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge / Endpoint Device.
Takanori IsonoMakoto YamakuraSatoshi ShimayaIsao KawamotoNobuhiro TsuboiMasaaki MineoWataru NakajimaKenichi IshidaShin SasakiToshio HiguchiMasahiro HoshakuDaisuke MurakamiToshifumi IwasakiHiroshi HiraiPublished in: A-SSCC (2020)
Keyphrases
- low power
- convolutional neural network
- power consumption
- low cost
- ultra low power
- high speed
- face detection
- single chip
- wireless transmission
- low power consumption
- digital signal processing
- logic circuits
- high power
- edge detection
- gate array
- vlsi architecture
- vlsi circuits
- image sensor
- neural network
- object detection
- delay insensitive
- power reduction
- cmos technology
- field programmable gate array