A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.
Florence AzaïsSerge BernardYves BertrandMichel RenovellPublished in: J. Electron. Test. (2001)
Keyphrases
- low cost
- real time
- neural network
- management system
- gray level
- digital camera
- low power
- hardware and software
- data flow
- architectural design
- highly efficient
- network architecture
- reconfigurable hardware
- layered architecture
- design considerations
- linear constraints
- associative memory
- closed form
- learning algorithm
- data sets