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A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS.
Bob Verbruggen
Jan Craninckx
Maarten Kuijk
Piet Wambacq
Geert Van der Plas
Published in:
IEEE J. Solid State Circuits (2010)
Keyphrases
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analog to digital converter
power consumption
low power
circuit design
metal oxide semiconductor
high speed
image sensor
power supply
cmos technology
hd video
clock gating
real time
neural network
low cost
nm technology
digital media