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Simulation of 0.35 μm/0.25 μm CMOS Technology Doping Profiles.

M. LorenziniLuc HaspeslaghJan Van HoudtH. E. Maes
Published in: VLSI Design (2001)
Keyphrases
  • cmos technology
  • low power
  • power consumption
  • low voltage
  • case study
  • parallel processing
  • real time
  • spl times