Login / Signup
Simulation of 0.35 μm/0.25 μm CMOS Technology Doping Profiles.
M. Lorenzini
Luc Haspeslagh
Jan Van Houdt
H. E. Maes
Published in:
VLSI Design (2001)
Keyphrases
</>
cmos technology
low power
power consumption
low voltage
case study
parallel processing
real time
spl times