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Statically triggered 3×VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process.
Zhaonian Yang
Yuan Yang
Ningmei Yu
Juin J. Liou
Published in:
Microelectron. J. (2018)
Keyphrases
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low voltage
cmos technology
power line
low power
design considerations
leakage current
power consumption
parallel processing
power management
object detection