A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter.
Brice LhommeYann CarminatiBertrand BorotOlivier CallenThierry BurdeauSylvain ClercPublished in: ESSCIRC (2010)
Keyphrases
- low voltage
- cmos technology
- random access memory
- low power
- power consumption
- leakage current
- high speed
- low cost
- nm technology
- embedded dram
- mixed signal
- parallel processing
- failure detection
- analog vlsi
- metal oxide semiconductor
- silicon on insulator
- knowledge base
- cmos image sensor
- power management
- real time
- image sensor
- power dissipation
- single chip
- circuit design
- design considerations
- monitoring system
- floating point
- dynamic random access memory