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Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.
Chiao-Ling Lung
Yu-Shih Su
Hsih-Hsiu Huang
Yiyu Shi
Shih-Chieh Chang
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
Keyphrases
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fault tolerant
fault tolerance
high speed
distributed systems
interconnection networks
social networks
low cost
load balancing
safety critical
power consumption
high availability
network structure
complex networks
data structure