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Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays.

Debjyoti BhattacharjeeAnne SiemonEike LinnStephan MenzelAnupam Chattopadhyay
Published in: MWSCAS (2016)
Keyphrases
  • efficient implementation
  • efficient processing
  • active set
  • hardware implementation
  • allocation scheme
  • highly parallel
  • response time