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A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth.
Zhiwei Li
Yan Li
Song Chen
Feng Wu
Published in:
ASICON (2017)
Keyphrases
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memory usage
hardware architecture
convolutional neural network
hardware implementation
face detection
memory footprint
memory requirements
hardware architectures
field programmable gate array
neural network
associative memory
feature selection
feature extraction
main memory
processing elements