Reliability-aware core partitioning in chip multiprocessors.

Isil Öz Haluk Rahmi Topcuoglu Mahmut T. Kandemir Oguz Tosun

Published in: J. Syst. Archit. (2012)

Keyphrases

multithreading
low cost
high speed
analog vlsi
reliability analysis
parallel implementation
high density
coalitional games
highly reliable
graph partitioning
image processing
information retrieval
real time
data partitioning
input output
case study
vlsi implementation
neural network