Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.
Tin Wai KwanMaitham ShamsPublished in: ASYNC (2005)
Keyphrases
- chip design
- high level synthesis
- delay insensitive
- asynchronous circuits
- digital circuits
- logic synthesis
- logic circuits
- power dissipation
- shift register
- design tools
- circuit design
- power reduction
- design space
- design methodology
- engineering design
- power consumption
- design process
- case study
- neural network
- current status
- design principles
- floating gate
- user interface