Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip.
Xiaohang WangMaurizio PalesiMei YangYingtao JiangMichael C. HuangPeng LiuPublished in: NPC (2011)
Keyphrases
- ibm power processor
- high speed
- high bandwidth
- chip design
- low cost
- power dissipation
- network structure
- power consumption
- complex networks
- network model
- computer networks
- bayesian networks
- vlsi implementation
- high density
- social networks
- host computer
- memory subsystem
- power management
- parallel processing
- network analysis
- incremental learning
- real time
- wireless sensor networks
- evolutionary algorithm
- neural network