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A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
Petar Jokic
Erfan Azarkhish
Andrea Bonetti
Marc Pons
Stéphane Emery
Luca Benini
Published in:
CoRR (2021)
Keyphrases
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low power
neural network
power consumption
low cost
high speed
single chip
high power
vlsi architecture
logic circuits
low power consumption
digital signal processing
image sensor
cmos technology
wireless transmission
vlsi circuits
delay insensitive
nm technology
gate array
ultra low power