A hierarchical, automated target recognition algorithm for a parallel analog processor.
Curtis PadgettGail WoodwardPublished in: CIRA (1997)
Keyphrases
- recognition algorithm
- parallel processing
- computer architecture
- distributed memory
- multi core processors
- single processor
- multiprocessor systems
- recognition process
- multi processor
- parallel implementation
- iris recognition
- parallel architecture
- level parallelism
- traffic signs
- instruction set
- human identification
- parallel architectures
- shared memory
- palmprint
- high speed
- shared memory multiprocessor
- decomposition algorithm
- parallel processors
- iris images
- active learning