High speed and low power on-chip micro network circuit with differential transmission line.
Shinichiro GomiKohichi NakamuraHiroyuki ItoHideyuki SugitaKenichi OkadaKazuya MasuPublished in: SoC (2004)
Keyphrases
- high speed
- low power
- transmission line
- cmos technology
- single chip
- low power consumption
- logic circuits
- power reduction
- power system
- content addressable memory
- power dissipation
- low cost
- digital signal processing
- real time
- mixed signal
- vlsi circuits
- neural network
- image sensor
- communication networks
- nm technology
- tunnel diode
- gate array
- ultra low power
- multi channel
- phase transition
- delay insensitive
- wireless sensor networks
- gigabit ethernet
- expert systems