A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference.
Yuansheng ZhaoZixuan ShenJiarui XuKevin C. T. ChaiYanqing WuChao WangPublished in: AICAS (2023)
Keyphrases
- memory subsystem
- embedded dram
- random access memory
- dynamic random access memory
- training process
- high density
- memory access
- main memory
- instruction set
- ibm zenterprise
- level parallelism
- cmos technology
- structured prediction
- multithreading
- inference engine
- vlsi implementation
- video decoder
- design considerations
- computational power
- resource manager
- host computer
- management system
- digital signal processors
- bayesian networks
- database systems
- parallel computing
- associative memory
- memory hierarchy
- memory requirements
- input output
- high speed
- training set
- data structure