Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.
Fabian OborilRajendra BishnoiMojtaba EbrahimiMehdi Baradaran TahooriPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
Keyphrases
- random access memory
- memory subsystem
- memory access
- main memory
- multithreading
- high speed
- design considerations
- query processing
- speculative execution
- processor core
- memory hierarchy
- low cost
- computational power
- data access
- data management
- memory management
- single chip
- memory bandwidth
- cache conscious
- prefetching
- dynamic random access memory